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An Embedded Coherent-Multithreading Multimedia Processor and Its Programming Model., , , , and . DAC, page 652-657. IEEE, (2007)Recognizing Chinese Texts with 3D Convolutional Neural Network., , , and . ICIP, page 2120-2123. IEEE, (2019)An efficient design for one-dimensional discrete Hartley transform using parallel additions.. IEEE Trans. Signal Process., 48 (10): 2806-2813 (2000)Real-Time 3D Depth Generation for Stereoscopic Video Applications with Thread-Level Superscalar-Pipeline Parallelization., , , and . J. Signal Process. Syst., 72 (1): 17-33 (2013)A Low-Power Parameterized Hardware Design for the One-Dimensional Discrete Fourier Transform of Variable Lengths., , and . Journal of Circuits, Systems, and Computers, 11 (4): 405-428 (2002)A Low Complexity High Quality Interger Motion Estimation Architecture Design for H.264/AVC., , , , , , and . APCCAS, page 398-401. IEEE, (2006)A power-aware IP core generator for the one-dimensional discrete Fourier transform., , , and . ISCAS (3), page 637-640. IEEE, (2004)A High Throughput Deblocking Filter Design Supporting Multiple Video Coding Standards., , and . ISCAS, page 2377-2380. IEEE, (2009)Design of a new signal security system., and . ISCAS (4), page 121-124. IEEE, (2002)A CORDIC-based VLSI Array for Computing 2-D Discrete Hartley Transform., , and . ISCAS, page 1571-1574. IEEE, (1993)