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Making System Level Test Possible by a Mixed-mode, Multi-level, Integrated Modeling Environment.

, , , , , and . EWDTS, page 1-5. IEEE, (2019)

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Reconfiguration of Embedded Accelerators by Microprogramming for Intensive Loop Computations., , , , , and . DDECS, page 1-4. IEEE, (2020)Reducing DFT hardware overhead by use of a test microprogram in a microprogrammed hardware accelerator., , , , , and . DFT, page 1-4. IEEE, (2020)An ESL Environment for Modeling Electrical Interconnect Faults., , , and . ISVLSI, page 88-93. IEEE, (2019)Back-annotation of Interconnect Physical Properties for System-Level Crosstalk Modeling., , , and . ETS, page 1-6. IEEE, (2019)Testing a RISCV-Like Architecture With an HDL-Based Virtual Tester., , , , and . DTIS, page 1-6. IEEE, (2021)Making System Level Test Possible by a Mixed-mode, Multi-level, Integrated Modeling Environment., , , , , and . EWDTS, page 1-5. IEEE, (2019)ESL, Back-annotating Crosstalk Fault Models into High-level Communication Links., , , and . VTS, page 1-6. IEEE, (2020)Learning Electrical Behavior of Core Interconnects for System-Level Crosstalk Prediction., , , , and . ETS, page 1-6. IEEE, (2023)Concurrent Error Detection for LSTM Accelerators., , , and . ETS, page 1-2. IEEE, (2022)Multi-Level Fault Injection Methodology Using UVM-SystemC., , , , and . EWDTS, page 1-6. IEEE, (2023)