( en | de | ru )

 

Disambiguation of "Navabi, Zainalabedin"

Author of the publication

copydeleteadd this publication to your clipboard
Learning Electrical Behavior of Core Interconnects for System-Level Crosstalk Prediction.

, , , , and . ETS, page 1-6. IEEE, (2023)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Kambiz Navabi

Foroogh Navabi-Kermani

 

Other publications of authors with the same name

SCOAP-based Directed Random Test Generation for Combinational Circuits., , , and . EWDTS, page 1-5. IEEE, (2019)An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements., , , , , , and . EWDTS, page 1-6. IEEE, (2019)Back-annotation of gate-level power properties into system level descriptions., and . NEWCAS, page 237-240. IEEE, (2014)A high-level language for design and modeling of hardware.. J. Syst. Softw., 18 (1): 5-18 (1992)A Low Power BIST Architecture for FPGA Look-Up Table Testing., and . VLSI-SOC, page 394-397. Technische Universität Darmstadt, Insitute of Microelectronic Systems, (2003)Using Verilog VPI for Mixed Level Serial Fault Simulation in a Test Generation Environment., , and . Embedded Systems and Applications, page 139-143. CSREA Press, (2003)Modeling Timing Behavior of Logic Circuits Using Piecewise Linear Models., , , and . CHDL, volume A-32 of IFIP Transactions, page 569-586. North-Holland, (1993)Programmable Routing Tables for Degradable Torus-Based Networks on Chips., , and . ISCAS, page 1065-1068. IEEE, (2007)An efficient BIST method for testing of embedded SRAMs., , and . ISCAS (5), page 73-76. IEEE, (2001)Near-Optimal Node Selection Procedure for Aging Monitor Placement., , and . IOLTS, page 6-11. IEEE, (2018)