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Disambiguation of "Yoshihara, Masahiro"

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A 120mm2 16Gb 4-MLC NAND Flash Memory with 43nm CMOS Technology.

, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , and . ISSCC, page 430-431. IEEE, (2008)

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Masahiro Noguchi

Masahiro Ogawa

Masahiro Yoshida

Masahiro Katsura

Masahiro Niitsuma

 

Other publications of authors with the same name

13.5 A 128Gb 1b/Cell 96-Word-Line-Layer 3D Flash Memory to Improve Random Read Latency with tPROG=75µs and tR=4µs., , , , , , , , , and 13 other author(s). ISSCC, page 226-228. IEEE, (2020)30.4 A 1Tb 3b/Cell 3D-Flash Memory in a 170+ Word-Line-Layer Technology., , , , , , , , , and 49 other author(s). ISSCC, page 428-430. IEEE, (2021)A 19nm 112.8mm2 64Gb multi-level flash memory with 400Mb/s/pin 1.8V Toggle Mode interface., , , , , , , , , and 45 other author(s). ISSCC, page 422-424. IEEE, (2012)An Effect of Inhibitory Connections on Synchronous Firing Assembly in the Inhibitory Connected Pulse Coupled Neural Network., , and . ICONIP (1), volume 6443 of Lecture Notes in Computer Science, page 179-187. Springer, (2010)A 120mm2 16Gb 4-MLC NAND Flash Memory with 43nm CMOS Technology., , , , , , , , , and 27 other author(s). ISSCC, page 430-431. IEEE, (2008)A 128Gb 1-bit/Cell 96-Word-Line-Layer 3D Flash Memory to Improve the Random Read Latency With tProg = 75 μs and tR = 4 μs., , , , , , , , , and 14 other author(s). IEEE J. Solid State Circuits, 56 (1): 225-234 (2021)