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Common Bonds: MIPS, HPS, Two-Level Branch Prediction, and Compressed Code RISC Processor., , , , , , , , , and 3 other author(s). IEEE Micro, 36 (4): 70-85 (2016)Improving Multi-Application Concurrency Support Within the GPU Memory System., , , , , , , and . CoRR, (2017)Reducing DRAM Latency by Exploiting Design-Induced Latency Variation in Modern DRAM Chips., , , , , , , and . CoRR, (2016)The Blacklisting Memory Scheduler: Balancing Performance, Fairness and Complexity., , , , and . CoRR, (2015)Predictable Performance and Fairness Through Accurate Slowdown Estimation in Shared Main Memory Systems., , , , and . CoRR, (2018)Simultaneous Multi Layer Access: A High Bandwidth and Low Cost 3D-Stacked Memory Interface., , , , and . CoRR, (2015)Understanding the effects of wrong-path memory references on processor performance., , , and . WMPI, page 56-64. ACM, (2004)Zwift: A Programming Framework for High Performance Text Analytics on Compressed Data., , , , and . ICS, page 195-206. ACM, (2018)In-DRAM Bulk Bitwise Execution Engine., and . CoRR, (2019)Dynamic Predication of Indirect Jumps., , , and . IEEE Comput. Archit. Lett., 6 (2): 25-28 (2007)