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RTL-Based Functional Test Generation for High Defects Coverage in Digital Systems.

, , , and . J. Electron. Test., 17 (3-4): 311-319 (2001)

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On the Analysis of Routing Cells and Adjacency Faults in CMOS Digital Circuits., , , and . DFT, page 263-270. IEEE Computer Society, (1994)Ultra low power capless LDO with dynamic biasing of derivative feedback., , , and . Microelectron. J., 44 (2): 94-102 (2013)Digital modular control of high frequency DC-DC converters., , and . Microelectron. J., 45 (10): 1254-1260 (2014)Modeling of Inherent Losses of Fully Integrated Switched Capacitor DC-DC Converters., , , and . J. Low Power Electron., 8 (5): 667-673 (2012)Low-sensitivity to process variations aging sensor for automotive safety-critical applications., , , , , , and . VTS, page 238-243. IEEE Computer Society, (2010)BIST Architectures and Fault Emulation., , and . LATW, page 55-60. IEEE, (2006)Monolithic Multi-mode DC-DC Converter with Gate Voltage Optimization., , , , and . PATMOS, volume 5349 of Lecture Notes in Computer Science, page 258-267. Springer, (2008)Aging-Aware Power or Frequency Tuning With Predictive Fault Detection., , , , , , , , and . IEEE Des. Test Comput., 29 (5): 27-36 (2012)RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage., , , and . J. Electron. Test., 18 (2): 179-187 (2002)Low Power BIST by Filtering Non-Detecting Vectors., , , , , , , , , and . J. Electron. Test., 16 (3): 193-202 (2000)