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Disambiguation of "Gauchi, Roman"

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Reconfigurable tiles of computing-in-memory SRAM architecture for scalable vectorization.

, , , , , , , and . ISLPED, page 121-126. ACM, (2020)

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Christoph Romanowski

Maria-Elena Romansky-Rieken

Georg Romanowski

Ute Romann

Olga Romanow

 

Other publications of authors with the same name

Memory Sizing of a Scalable SRAM In-Memory Computing Tile Based Architecture., , , , , , and . VLSI-SoC, page 166-171. IEEE, (2019)Secure eFPGA Configuration: A System-Level Approach., , and . ARC, volume 14553 of Lecture Notes in Computer Science, page 151-165. Springer, (2024)An Energy-Efficient Three-Independent-Gate FET Cell Library for Low-Power Edge Computing., , and . VLSI-SoC, page 1-6. IEEE, (2022)Storage Class Memory with Computing Row Buffer: A Design Space Exploration., , , , , , , , , and . DATE, page 1-6. IEEE, (2021)An Open-source Three-Independent-Gate FET Standard Cell Library for Mixed Logic Synthesis., , and . ISCAS, page 273-277. IEEE, (2022)Towards a Truly Integrated Vector Processing Unit for Memory-bound Applications Based on a Cost-competitive Computational SRAM Design Solution., , , , , , , , and . ACM J. Emerg. Technol. Comput. Syst., 18 (2): 40:1-40:26 (2022)Computational SRAM Design Automation using Pushed-Rule Bitcells for Energy-Efficient Vector Processing., , , , , , , and . DATE, page 1187-1192. IEEE, (2020)Smart-Redundancy With In Memory ECC Checking: Low-Power SEE-Resistant FPGA Architectures., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 31 (8): 1204-1213 (August 2023)Low Latency SEU Detection in FPGA CRAM With In-Memory ECC Checking., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (5): 2028-2036 (May 2023)Reconfigurable tiles of computing-in-memory SRAM architecture for scalable vectorization., , , , , , , and . ISLPED, page 121-126. ACM, (2020)