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A Reconfigurable Parallel Disk System for Filtering Genomic Banks., , , and . Engineering of Reconfigurable Systems and Algorithms, page 154-166. CSREA Press, (2003)Efficient hardware implementation of data-flow parallel embedded systems., , and . ICSAMOS, page 364-371. IEEE, (2012)Superword level parallelism aware word length optimization., and . DATE, page 1068-1073. IEEE, (2017)GeCoS: A framework for prototyping custom hardware design flows., , , , , , , , , and 3 other author(s). SCAM, page 100-105. IEEE Computer Society, (2013)FCCMS and the Memory Wall., and . FCCM, page 329-330. IEEE Computer Society, (2000)Ultra Low-power FSM for Control Oriented Applications., , and . ISCAS, page 1577-1580. IEEE, (2009)A semiempirical model for wakeup time estimation in power-gated logic clusters., , and . DAC, page 48-55. ACM, (2012)Hybrid-DBT: Hardware/Software Dynamic Binary Translation Targeting VLIW., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (10): 1872-1885 (2019)Enabling Overclocking Through Algorithm-Level Error Detection., , and . FPT, page 174-181. IEEE, (2018)Using polyhedral techniques to tighten WCET estimates of optimized code: A case study with array contraction., , , , , , and . DATE, page 925-930. IEEE, (2018)