Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks.

J. Kim, C. Nicopoulos, D. Park, V. Narayanan, M. Yousif, and C. Das. ISCA, page 4-15. IEEE Computer Society, (2006)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Rosemary Park

Sungjune Park

Jinhyung Park

Kwan Park

Shinja Park

Other publications of authors with the same name

On the Effects of Process Variation in Network-on-Chip Architectures.C. Nicopoulos, S. Srinivasan, A. Yanamandra, D. Park, V. Narayanan, C. Das, and M. Irwin. IEEE Trans. Dependable Secur. Comput., 7 (3): 240-254 (2010)ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers.C. Nicopoulos, D. Park, J. Kim, N. Vijaykrishnan, M. Yousif, and C. Das. MICRO, page 333-346. IEEE Computer Society, (2006)MIRA: A Multi-layered On-Chip Interconnect Router Architecture.D. Park, S. Eachempati, R. Das, A. Mishra, Y. Xie, N. Vijaykrishnan, and C. Das. ISCA, page 251-261. IEEE Computer Society, (2008)MoDe-X: Microarchitecture of a Layout-Aware Modular Decoupled Crossbar for On-Chip Interconnects.D. Park, A. Vaidya, A. Kumar, and M. Azimi. IEEE Trans. Computers, 63 (3): 622-636 (2014)Performance and power optimization through data compression in Network-on-Chip architectures.R. Das, A. Mishra, C. Nicopoulos, D. Park, V. Narayanan, R. Iyer, M. Yousif, and C. Das. HPCA, page 215-225. IEEE Computer Society, (2008)A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks.T. Richardson, C. Nicopoulos, D. Park, N. Vijaykrishnan, Y. Xie, C. Das, and V. Degalahal. VLSI Design, page 657-664. IEEE Computer Society, (2006)A novel dimensionally-decomposed router for on-chip communication in 3D architectures.J. Kim, C. Nicopoulos, D. Park, R. Das, Y. Xie, N. Vijaykrishnan, M. Yousif, and C. Das. ISCA, page 138-149. ACM, (2007)A Distributed Multi-Point Network Interface for Low-Latency, Deadlock-Free On-Chip Interconnects.D. Park, C. Nicopoulos, J. Kim, N. Vijaykrishnan, and C. Das. Nano-Net, page 1-6. IEEE, (2006)A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks.J. Kim, C. Nicopoulos, D. Park, V. Narayanan, M. Yousif, and C. Das. ISCA, page 4-15. IEEE Computer Society, (2006)FPGA-based prototyping of a 2D MESH / TORUS on-chip interconnect (abstract only).D. Dai, A. Vaidya, R. Saharoy, S. Park, D. Park, H. Thantry, R. Plate, E. Maas, A. Kumar, and M. Azimi. FPGA, page 293. ACM, (2010)

BibSonomy

Disambiguation of "Park, Dongkook"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks.

Please choose a person to relate this publication to

Rosemary Park

Sungjune Park

Jinhyung Park

Kwan Park

Shinja Park

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Park, Dongkook"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks.

Please choose a person to relate this publication to

Rosemary Park

Sungjune Park

Jinhyung Park

Kwan Park

Shinja Park

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks.