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A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks.

J. Kim, C. Nicopoulos, D. Park, V. Narayanan, M. Yousif, and C. Das. ISCA, page 4-15. IEEE Computer Society, (2006)

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P Narayanan

Hermine Narayanan

Vidya Narayanan

Narayanan Radhakrishnan

Narayanan Sundaram

Other publications of authors with the same name

Process-Variation-Aware Adaptive Cache Architecture and Management.M. Mutyam, F. Wang, K. Ramakrishnan, V. Narayanan, M. Kandemir, Y. Xie, and M. Irwin. IEEE Trans. Computers, 58 (7): 865-877 (2009)A reconfigurable platform for the design and verification of domain-specific accelerators.S. Park, Y. Cho, K. Irick, and V. Narayanan. ASP-DAC, page 108-113. IEEE, (2012)A scalable architecture for multi-class visual object detection.S. Advani, Y. Tanabe, K. Irick, J. Sampson, and V. Narayanan. FPL, page 1-8. IEEE, (2015)A hardware accelerated multilevel visual classifier for embedded visual-assist systems.M. Cotter, S. Advani, J. Sampson, K. Irick, and V. Narayanan. ICCAD, page 96-100. IEEE, (2014)Clone Detection in Sensor Networks with Ad Hoc and Grid Topologies.R. Brooks, P. Govindaraju, M. Pirretti, N. Vijaykrishnan, and M. Kandemir. IJDSN, 5 (3): 209-223 (2009)A task-oriented vision system.Y. Xiao, K. Irick, J. Sampson, V. Narayanan, and C. Zhang. ACM Great Lakes Symposium on VLSI, page 181-186. ACM, (2014)A comparative study of power efficient SRAM designs.J. Hezavei, N. Vijaykrishnan, and M. Irwin. ACM Great Lakes Symposium on VLSI, page 117-122. ACM, (2000)A Monolithic-3D SRAM Design with Enhanced Robustness and In-Memory Computation Support.S. Srinivasa, A. Ramanathan, X. Li, W. Chen, F. Hsueh, C. Yang, C. Shen, J. Shieh, S. Gupta, M. Chang and 3 other author(s). ISLPED, page 34:1-34:6. ACM, (2018)Noise Aware Power Adaptive Partitioned Deep Networks for Mobile Visual Assist Platforms.P. Zientara, J. Sampson, and V. Narayanan. SoCC, page 186-191. IEEE, (2018)Using complete system simulation to characterize SPECjvm98 benchmarks.T. Li, L. John, N. Vijaykrishnan, A. Sivasubramaniam, J. Sabarinathan, and A. Murthy. ICS, page 22-33. ACM, (2000)

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Disambiguation of "Narayanan, Vijaykrishnan"

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A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks.

Please choose a person to relate this publication to

P Narayanan

Hermine Narayanan

Vidya Narayanan

Narayanan Radhakrishnan

Narayanan Sundaram

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Narayanan, Vijaykrishnan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks.

Please choose a person to relate this publication to

P Narayanan

Hermine Narayanan

Vidya Narayanan

Narayanan Radhakrishnan

Narayanan Sundaram

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks.