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An Architecture for Motion Estimation in the Transform Domain.

, , , and . VLSI Design, page 1077-1082. IEEE Computer Society, (2004)

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Mesh Arrays and LOGICIAN: A Tool for Their Efficient Generation., , and . DAC, page 357-362. IEEE Computer Society Press / ACM, (1987)Process-Variation-Aware Adaptive Cache Architecture and Management., , , , , , and . IEEE Trans. Computers, 58 (7): 865-877 (2009)Exploiting communication complexity for multilevel logic synthesis., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 9 (10): 1017-1027 (1990)Efficiently computing communication complexity for multilevel logic synthesis., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 11 (5): 545-554 (1992)Secretary/Treasurer's Report.. SIGARCH Comput. Archit. News, 14 (4): 28 (1986)A hybrid NoC design for cache coherence optimization for chip multiprocessors., , , , , and . DAC, page 834-842. ACM, (2012)Reduction of broadband noise in speech by spectral weighting.. ICASSP, page 1045-1051. IEEE, (1980)Using Memory Compression for Energy Reduction in an Embedded Java System., , , , and . Journal of Circuits, Systems, and Computers, 11 (5): 537-556 (2002)Accurate Estimation of Combinational Circuit Activity., , , and . DAC, page 618-622. ACM Press, (1995)Validation of an Architectural Level Power Analysis Technique., , , and . DAC, page 242-245. ACM Press, (1998)