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Reducing instruction cache energy consumption using a compiler-based strategy.

, , , , , и . ACM Trans. Archit. Code Optim., 1 (1): 3-33 (2004)

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Jane Mary Schröder

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Ryan Irwin

 

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Accurate Estimation of Combinational Circuit Activity., , , и . DAC, стр. 618-622. ACM Press, (1995)Validation of an Architectural Level Power Analysis Technique., , , и . DAC, стр. 242-245. ACM Press, (1998)Exploring performance-power tradeoffs in providing reliability for NoC-based MPSoCs., , и . ISQED, стр. 495-501. IEEE, (2011)Process-Variation-Aware Adaptive Cache Architecture and Management., , , , , , и . IEEE Trans. Computers, 58 (7): 865-877 (2009)Number representations for reducing switched capacitance in subband coding., и . ICASSP, стр. 3125-3128. IEEE, (1998)A rational arithmetic processor., и . IEEE Symposium on Computer Arithmetic, стр. 241-244. IEEE Computer Society, (1981)A new optimization driven clustering algorithm for large circuits., , и . EURO-DAC, стр. 28-32. IEEE Computer Society, (1993)Multi-way FSM decomposition based on interconnect complexity., , и . EURO-DAC, стр. 390-395. IEEE Computer Society, (1993)The design and implementation of the Arithmetic Cube II, a VLSI signal processing system., , , , , и . IEEE Trans. Very Large Scale Integr. Syst., 1 (4): 491-502 (1993)The design of the MGAP-2: a micro-grained massively parallel array., , , и . IEEE Trans. Very Large Scale Integr. Syst., 8 (6): 709-716 (2000)