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Disambiguation of "Carlson, Trevor E."

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An Evaluation of High-Level Mechanistic Core Models.

, , , , and . ACM Trans. Archit. Code Optim., 11 (3): 28:1-28:25 (2014)

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Trevor Hansen

Trevor Jones

Gustav Carlson

Christopher Carlson

Trevor Collins

 

Other publications of authors with the same name

System-level power/performance evaluation of 3D stacked DRAMs for mobile applications., , , , , , , and . DATE, page 923-928. IEEE, (2009)Evaluating Application Vulnerability to Soft Errors in Multi-level Cache Hierarchy., , , and . Euro-Par Workshops (2), volume 7156 of Lecture Notes in Computer Science, page 272-281. Springer, (2011)SOTERIA: In Search of Efficient Neural Networks for Private Inference., , , and . CoRR, (2020)Maximizing Limited Resources: a Limit-Based Study and Taxonomy of Out-of-Order Commit., , , and . J. Signal Process. Syst., 91 (3-4): 379-397 (2019)Efficient Instruction Scheduling using Real-time Load Delay Tracking., and . CoRR, (2021)Rectified Linear Postsynaptic Potential Function for Backpropagation in Deep Spiking Neural Networks., , , , , , , , , and 1 other author(s). IEEE Trans. Neural Networks Learn. Syst., 33 (5): 1947-1958 (2022)Sentry-NoC: a statically-scheduled NoC for secure SoCs., , , and . NOCS, page 67-74. ACM, (2021)HidFix: Efficient Mitigation of Cache-Based Spectre Attacks Through Hidden Rollbacks., , and . ICCAD, page 1-9. IEEE, (2023)Non-Speculative Load-Load Reordering in TSO., , , and . ISCA, page 187-200. ACM, (2017)Micro-architecture independent analytical processor performance and power modeling., , , , , , , and . ISPASS, page 32-41. IEEE Computer Society, (2015)