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YAPPA: A compiler-based parallelization framework for irregular applications on MPSoCs.

, , , и . RSP, стр. 123-129. IEEE, (2013)

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Fabrizio Catanese

Fabrizio Gabbiani

Fabrizio Gabrielli

Fabrizio Lindner

Fabrizio Arosio

 

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Symbolic Optimization of FSM Networks Based on Sequential ATPG Techniques., , , , и . DAC, стр. 467-470. ACM Press, (1996)SYNAPTIC Project: Regularity Applied to Enhance Manufacturability and Yield at Several Abstraction Levels., , , , , , , , , и 3 other автор(ы). ARCS Workshops, VDE-Verlag, (2011)Bambu: A modular framework for the high level synthesis of memory-intensive applications., и . FPL, стр. 1-4. IEEE, (2013)HArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms., , , , , , , , , и 1 other автор(ы). IEEE Micro, 30 (5): 88-97 (2010)Performance modeling of embedded applications with zero architectural knowledge., и . CODES+ISSS, стр. 277-286. ACM, (2010)Symbolic optimization of interacting controllers based onredundancy identification and removal., , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 19 (7): 760-772 (2000)Reduction of Fault Detection Costs through Testable Design of Sequential Architectures with Signal Feedbacks., , , , , и . DFT, стр. 223-230. IEEE Computer Society, (1993)An Expert Solution to Functional Testability Analysis of VLSI Circuits., , , , , и . SEKE, стр. 263-265. Knowledge Systems Institute, (1993)A design methodology to implement memory accesses in high-level synthesis., , и . CODES+ISSS, стр. 49-58. ACM, (2011)An Interrupt Controller for FPGA-based Multiprocessors., , , , , , и . ICSAMOS, стр. 82-87. IEEE, (2007)