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Dynamic Power Management for Neuromorphic Many-Core Systems., , , , , , , , , and 5 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (8): 2973-2986 (2019)10.7 A 105GOPS 36mm2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS., , , , , , , , , and 7 other author(s). ISSCC, page 188-189. IEEE, (2014)Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems., , , , , , , , , and 10 other author(s). ISCAS, page 1. IEEE, (2017)The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing., , , , , , , , , and 8 other author(s). CoRR, (2021)Dynamic Power Management for Neuromorphic Many-Core Systems., , , , , , , , , and 5 other author(s). CoRR, (2019)Dynamic voltage and frequency scaling for neuromorphic many-core systems., , , , , , , , , and 9 other author(s). ISCAS, page 1-4. IEEE, (2017)