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Disambiguation of "Fuketa, Hiroshi"

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24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in VDDmin limited ultra low voltage logic circuits.

, , , , , , , , , , , and . ISQED, page 586-591. IEEE, (2012)

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Hiroshi Kawabe

Hiroshi Murata

Hiroshi Kubota

Hiroshi Uchida

Hiroshi Fukuzaki

 

Other publications of authors with the same name

Intermittent resonant clocking enabling power reduction at any clock frequency for 0.37V 980kHz near-threshold logic circuits., , , and . ISSCC, page 436-437. IEEE, (2013)Image-Classifier Deep Convolutional Neural Network Training by 9-bit Dedicated Hardware to Realize Validation Accuracy and Energy Efficiency Superior to the Half Precision Floating Point Format., , , , , , and . ISCAS, page 1-5. IEEE, (2018)92% start-up time reduction by variation-tolerant chirp injection (CI) and negative resistance booster (NRB) in 39MHz crystal oscillator., , , and . VLSIC, page 1-2. IEEE, (2014)Transistor Variability Modeling and its Validation With Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits., , , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (7): 1118-1129 (2010)Analysis to optimize sensitivity of RF energy harvester with voltage boost circuit., , , , , and . ECCTD, page 1-4. IEEE, (2015)Wireless Power Transfer With Zero-Phase-Difference Capacitance Control., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (4): 938-947 (2015)Insole Pedometer With Piezoelectric Energy Harvester and 2 V Organic Circuits., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 48 (1): 255-264 (2013)Origin of Low-Frequency Noise in Si n-MOSFET at Cryogenic Temperatures: The Effect of Interface Quality., , , , , , , and . IEEE Access, (2023)Experimental study on body-biasing layout style-- negligible area overhead enables sufficient speed controllability --., , , , and . ACM Great Lakes Symposium on VLSI, page 387-390. ACM, (2008)12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (VDD) scaling from 1.2v to 310mv enabled by contention-less flip-flops (CLFF) and separated VDD between flip-flops and combinational logics., , , , , , and . ISLPED, page 163-168. IEEE/ACM, (2011)