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ILP Based Approach for Input Vector Controlled (IVC) Toggle Maximization in Combinational Circuits., , and . VDAT, volume 7373 of Lecture Notes in Computer Science, page 172-179. Springer, (2012)A Technique for Electrical Error Localization with Learning Methods During Post-silicon Debugging., , and . IGSC, page 1-8. IEEE, (2018)Using MISR as Countermeasure Against Scan-Based Side-Channel Attacks., , , and . EWDTS, page 1-6. IEEE, (2018)Impact of process variations on computers used for image processing., , , and . ISCAS, page 1444-1447. IEEE, (2012)SEU tolerant SRAM cell., , , , and . ISQED, page 597-602. IEEE, (2011)Instruction-Based Delay Fault Self-Testing of Processor Cores., , , and . VLSI Design, page 933-. IEEE Computer Society, (2004)A Soft Error Resilient Low Leakage SRAM Cell Design., , and . ATS, page 133-138. IEEE Computer Society, (2015)DAAIP: Deadblock Aware Adaptive Insertion Policy for High Performance Caching., , , and . ICCD, page 345-352. IEEE Computer Society, (2017)Observability calculation of state variable oriented to robust PDFs and LOC or LOS techniques., , , and . EWDTS, page 1-6. IEEE Computer Society, (2013)Fault grading using Instruction-Execution graph., , , and . EWDTS, page 350-357. IEEE Computer Society, (2010)