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Disambiguation of "Fujisawa, Hiroki"

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A low-impedance open-bitline array for multigigabit DRAM.

, , , , , , , and . IEEE J. Solid State Circuits, 37 (4): 487-498 (2002)

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Hiroki Takahashi

Hiroki Kawamura

Hiroki Sumizawa

 

Other publications of authors with the same name

A multigigabit DRAM technology with 6F2 open-bitline cell, distributed overdriven sensing, and stacked-flash fuse., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 36 (11): 1721-1727 (2001)A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 38 (5): 762-768 (2003)A dual-phase-controlled dynamic latched amplifier for high-speed and low-power DRAMs., , , and . IEEE J. Solid State Circuits, 36 (7): 1120-1126 (2001)A low-impedance open-bitline array for multigigabit DRAM., , , , , , , and . IEEE J. Solid State Circuits, 37 (4): 487-498 (2002)An 8.4ns Column-Access 1.3Gb/s/pin DDR3 SDRAM with an 8: 4 Multiplexed Data-Transfer Scheme., , , , , , , , , and 2 other author(s). ISSCC, page 557-566. IEEE, (2006)An 8.1-ns Column-Access 1.6-Gb/s/pin DDR3 SDRAM With an 8: 4 Multiplexed Data-Transfer Scheme., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 42 (1): 201-209 (2007)1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 40 (4): 862-869 (2005)The charge-share modified (CSM) precharge-level architecture for high-speed and low-power ferroelectric memory., , , , , and . IEEE J. Solid State Circuits, 32 (5): 655-661 (1997)