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Disambiguation of "Kohama, Yoshinori"

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3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link.

, , , , , , , , , , , , and . IEEE J. Solid State Circuits, 45 (4): 856-862 (2010)

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Yoshinori Aso

 

Other publications of authors with the same name

Modeling and Experimental Verification of Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for Low-Power 3-D System Integration., , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (8): 1238-1243 (2010)2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking., , , , , , , and . IEEE J. Solid State Circuits, 45 (1): 134-141 (2010)MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link., , , , , , , , , and 2 other author(s). FPL, page 6-11. IEEE, (2009)3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 45 (4): 856-862 (2010)A 2Gb/s 15pJ/b/chip Inductive-Coupling programmable bus for NAND Flash memory stacking., , , , , , , and . ISSCC, page 244-245. IEEE, (2009)A High-Speed Inductive-Coupling Link With Burst Transmission., , , , , and . IEEE J. Solid State Circuits, 44 (3): 947-955 (2009)47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking., , , , , , and . CICC, page 449-452. IEEE, (2009)An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM., , , , , , , , , and 3 other author(s). ISSCC, page 480-481. IEEE, (2009)Analysis and Techniques for Mitigating Interference From Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3-D System Integration., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 19 (10): 1902-1907 (2011)An 11Gb/s Inductive-Coupling Link with Burst Transmission., , , , , and . ISSCC, page 298-299. IEEE, (2008)