Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Transparent SOC: on-chip analyzing techniques and implementation for embedded processor., , , , and . SoCC, page 51-54. IEEE, (2004)Soft-Error-Tolerant Dual-Modular-Redundancy Architecture with Repair and Retry Scheme for Memory-Control Circuit on FPGA., , and . IEICE Trans. Electron., 100-C (4): 382-390 (2017)An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM., , , , , , , , , and 3 other author(s). ISSCC, page 480-481. IEEE, (2009)Scalable robotic-hand control system based on a hierarchical multi-processor architecture adopting a large number of tactile sensors., , and . IROS, page 14-19. IEEE, (2012)3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 45 (4): 856-862 (2010)Embedded SoC Resource Manager to Control Temperature and Data Bandwidth., , , , , , , , , and 3 other author(s). ISSCC, page 296-604. IEEE, (2007)A Low-Power Wide-Range Clock Synchronizer With Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS., , , , , and . IEEE J. Solid State Circuits, 45 (11): 2312-2320 (2010)Elastic shared resource scheduling SOC interconnect architecture for real-time system., , , , , , , , , and 1 other author(s). CICC, page 787-790. IEEE, (2005)Hierarchical 3D interconnection architecture with tightly-coupled processor-memory integration., , , , and . 3DIC, page 1-6. IEEE, (2010)