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Disambiguation of "Irie, Naohiko"

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3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link.

, , , , , , , , , , , , and . IEEE J. Solid State Circuits, 45 (4): 856-862 (2010)

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Robert Irie

 

Other publications of authors with the same name

Embedded SoC Resource Manager to Control Temperature and Data Bandwidth., , , , , , , , , and 3 other author(s). ISSCC, page 296-604. IEEE, (2007)3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 45 (4): 856-862 (2010)Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 42 (1): 74-83 (2007)Multi-Core/Multi-IP Technology for Embedded Applications., and . IEICE Trans. Electron., 92-C (10): 1232-1239 (2009)Modeling and Experimental Verification of Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for Low-Power 3-D System Integration., , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (8): 1238-1243 (2010)Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor., , , , , , , , , and 3 other author(s). ISSCC, page 2200-2209. IEEE, (2006)SIMP (Single Instruction stream/Multiple Instruction Pipelining): A Novel High-Speed Single-Processor Architecture., , , and . ISCA, page 78-85. ACM, (1989)A Hardware Accelerator for JavaTM Platforms on a 130-nm Embedded Processor Core., , , , , , , and . IEICE Trans. Electron., 90-C (2): 523-530 (2007)Elastic shared resource scheduling SOC interconnect architecture for real-time system., , , , , , , , , and 1 other author(s). CICC, page 787-790. IEEE, (2005)Analysis and Techniques for Mitigating Interference From Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3-D System Integration., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 19 (10): 1902-1907 (2011)