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A fast resolving BiNMOS synchronizer for parallel processor interconnect., and . IEEE J. Solid State Circuits, 30 (2): 133-139 (February 1995)An asynchronous instruction length decoder., , , , , , , , and . IEEE J. Solid State Circuits, 36 (2): 217-228 (2001)Intel's digital random number generator (DRNG)., , and . Hot Chips Symposium, page 1-13. IEEE, (2011)A 900 Mb/s bidirectional signaling scheme., , and . IEEE J. Solid State Circuits, 30 (12): 1538-1543 (December 1995)Miller and noise effects in a synchronizing flip-flop., and . IEEE J. Solid State Circuits, 34 (6): 849-855 (1999)RAPPID: An Asynchronous Instruction Length Decoder., , , , , , , , , and . ASYNC, page 60-70. IEEE Computer Society, (1999)Measuring Deep Metastability and Its Effect on Synchronizer Performance., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 15 (9): 1028-1039 (2007)On-Chip Measurement of Deep Metastability in Synchronizers., , , , and . IEEE J. Solid State Circuits, 43 (2): 550-557 (2008)