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Enabling Cutting-Edge Semiconductor Simulation through Grid Technology.

, , , , , , , and . LSSC, volume 5910 of Lecture Notes in Computer Science, page 369-378. Springer, (2009)

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Accurate simulations of the interplay between process and statistical variability for nanoscale FinFET-based SRAM cell stability., , , , and . ESSDERC, page 349-352. IEEE, (2014)Enabling Cutting-Edge Semiconductor Simulation through Grid Technology., , , , , , , and . LSSC, volume 5910 of Lecture Notes in Computer Science, page 369-378. Springer, (2009)Evaluating the accuracy of SRAM margin simulation through large scale Monte-Carlo simulations with accurate compact models., , , , , and . ICICDT, page 29-32. IEEE, (2013)TCAD based Design-Technology Co-Optimisations in advanced technology nodes., , , , , and . VLSI-DAT, page 1-2. IEEE, (2017)Circuit design perspectives for Ge FinFET at 10nm and beyond., , , , , , , , , and 2 other author(s). ISQED, page 57-60. IEEE, (2015)An advanced statistical compact model strategy for SRAM simulation at reduced VDD., , , , and . ESSDERC, page 205-208. IEEE, (2012)Progress on carbon nanotube BEOL interconnects., , , , , , , , , and 11 other author(s). DATE, page 937-942. IEEE, (2018)SRAM device and cell co-design considerations in a 14nm SOI FinFET technology., , , , , , , and . ISCAS, page 2339-2342. IEEE, (2013)Modeling and simulation of transistor and circuit variability and reliability., , , , , , , , and . CICC, page 1-8. IEEE, (2010)Impact of statistical variability and charge trapping on 14 nm SOI FinFET SRAM cell stability., , , , , , and . ESSDERC, page 234-237. IEEE, (2013)