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Core tunneling: Variation-aware voltage noise mitigation in GPUs.

, , , , and . HPCA, page 151-162. IEEE Computer Society, (2016)

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Mitigating the Effects of Process Variation in Ultra-low Voltage Chip Multiprocessors using Dual Supply Voltages and Half-Speed Units., , and . IEEE Comput. Archit. Lett., 11 (2): 45-48 (2012)Core tunneling: Variation-aware voltage noise mitigation in GPUs., , , , and . HPCA, page 151-162. IEEE Computer Society, (2016)Snatch: Opportunistically reassigning power allocation between processor and memory in 3D stacks., , , , , , , , and . MICRO, page 54:1-54:12. IEEE Computer Society, (2016)Parichute: Generalized Turbocode-Based Error Correction for Near-Threshold Caches., , , , and . MICRO, page 351-362. IEEE Computer Society, (2010)VRSync: Characterizing and eliminating synchronization-induced voltage emergencies in many-core processors., , , and . ISCA, page 249-260. IEEE Computer Society, (2012)EmerGPU: Understanding and mitigating resonance-induced voltage noise in GPU architectures., , and . ISPASS, page 79-89. IEEE Computer Society, (2016)Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chips., , , , and . HPCA, page 27-38. IEEE Computer Society, (2012)StVEC: A Vector Instruction Extension for High Performance Stencil Computation., , , , and . PACT, page 276-287. IEEE Computer Society, (2011)