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Accurate Estimation of Combinational Circuit Activity., , , and . DAC, page 618-622. ACM Press, (1995)Validation of an Architectural Level Power Analysis Technique., , , and . DAC, page 242-245. ACM Press, (1998)Exploring performance-power tradeoffs in providing reliability for NoC-based MPSoCs., , and . ISQED, page 495-501. IEEE, (2011)Process-Variation-Aware Adaptive Cache Architecture and Management., , , , , , and . IEEE Trans. Computers, 58 (7): 865-877 (2009)Number representations for reducing switched capacitance in subband coding., and . ICASSP, page 3125-3128. IEEE, (1998)A rational arithmetic processor., and . IEEE Symposium on Computer Arithmetic, page 241-244. IEEE Computer Society, (1981)A new optimization driven clustering algorithm for large circuits., , and . EURO-DAC, page 28-32. IEEE Computer Society, (1993)Multi-way FSM decomposition based on interconnect complexity., , and . EURO-DAC, page 390-395. IEEE Computer Society, (1993)The design and implementation of the Arithmetic Cube II, a VLSI signal processing system., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 1 (4): 491-502 (1993)The design of the MGAP-2: a micro-grained massively parallel array., , , and . IEEE Trans. Very Large Scale Integr. Syst., 8 (6): 709-716 (2000)