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Mitigating Memory Wall Effects in High-Clock-Rate and Multicore CMOS 3-D Processor Memory Stacks.

, , , , , , , , and . Proc. IEEE, 97 (1): 108-122 (2009)

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A High Speed Reconfigurable Gate Array for Gigahertz Applications., , , , , and . ISVLSI, page 124-129. IEEE Computer Society, (2005)3D direct vertical interconnect microprocessors test vehicle., , , , , and . ACM Great Lakes Symposium on VLSI, page 141-146. ACM, (2003)Gigahertz FPGA by SiGe BiCMOS Technology for Low Power, High Speed Computing with 3-D Memory., , , , , , , , , and . FPL, volume 2778 of Lecture Notes in Computer Science, page 11-20. Springer, (2003)Predicting the Performance of a 3D Processor-Memory Chip Stack., , , , , and . IEEE Des. Test Comput., 22 (6): 540-547 (2005)SiGe HBT Microprocessor Core Test Vehicle., , , and . Proc. IEEE, 93 (9): 1669-1678 (2005)Design of High-Speed Register Files Using SiGe HBT BiCMOS Technology., , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 61-II (3): 178-182 (2014)A three-port pipelined register file implemented using a SiGe HBT BiCMOS technology.. Rensselaer Polytechnic Institute, USA, (2006)The gigahertz FPGA: design consideration and applications., , , , , , , , , and . FPGA, page 248. ACM, (2004)