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Disambiguation of "Han, Kyuseung"

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TEI-NoC: Optimizing Ultralow Power NoCs Exploiting the Temperature Effect Inversion.

, , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (2): 458-471 (2018)

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Johannes Han

Bing Han

Mei Han

Luyang Han

Muxin Han

 

Other publications of authors with the same name

K-means Clustering-specific Lightweight RISC-V processor., , , , , , , and . ISOCC, page 391-392. IEEE, (2021)TIP: A Temperature Effect Inversion-Aware Ultra-Low Power System-on-Chip Platform., , , , and . ISLPED, page 1-6. IEEE, (2019)A Diagnosable Network-on-Chip for FPGA Verification of Intellectual Properties., , , and . IEEE Des. Test, 36 (2): 81-87 (2019)Coarse-grained reconfigurable architecture for multiple application domains: a case study., , , , , , and . ICHIT, volume 321 of ACM International Conference Proceeding Series, page 546-553. ACM, (2009)Florian: Developing a Low-Power RISC-V Multicore Processor with a Shared Lightweight FPU., , , , , , and . ISLPED, page 1-6. IEEE, (2023)A host-accelerator communication architecture design for efficient binary acceleration., , and . ISOCC, page 361-364. IEEE, (2011)TEI-ULP: Exploiting Body Biasing to Improve the TEI-Aware Ultralow Power Methods., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (9): 1758-1770 (2019)Software-Level Approaches for Tolerating Transient Faults in a Coarse-GrainedReconfigurable Architecture., , and . IEEE Trans. Dependable Secur. Comput., 11 (4): 392-398 (2014)Developing an Ultra-low Power RISC-V Processor for Anomaly Detection., , , , , and . DATE, page 1-2. IEEE, (2023)Enhancing Utilization of Integer Functional Units for High-Throughput Floating Point Operations on Coarse-Grained Reconfigurable Architecture., , and . MUE, volume 240 of Lecture Notes in Electrical Engineering, page 1161-1167. Springer, (2013)