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Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips.

, , , , , , , , , и . IEEE Micro, 31 (6): 6-18 (2011)

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Daisuke Yoshida

Daisuke Shibata

Daisuke Akimoto

Daisuke Mashima

Daisuke Shimizu

 

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Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units., , , , , , и . IPSJ Trans. Syst. LSI Des. Methodol., (2011)Cool Mega-Array: A highly energy efficient reconfigurable accelerator., , , , , , , , , и . FPT, стр. 1-8. IEEE, (2011)On-chip detection methodology for break-even time of power gated function units., , , , , , и . ISLPED, стр. 241-246. IEEE/ACM, (2011)Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs., , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (4): 520-533 (2011)Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating., , , , , , , , , и 6 other автор(ы). ASP-DAC, стр. 369-370. IEEE, (2010)A Leakage Efficient Instruction TLB Design for Embedded Processors., , , , , и . IEICE Trans. Inf. Syst., 94-D (8): 1565-1574 (2011)Adaptive power gating for function units in a microprocessor., , , , , , , , и . ISQED, стр. 29-37. IEEE, (2010)A Leakage Efficient Data TLB Design for Embedded Processors., , , , , и . IEICE Trans. Inf. Syst., 94-D (1): 51-59 (2011)Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips., , , , , , , , , и . IEEE Micro, 31 (6): 6-18 (2011)Geyser-2: The second prototype CPU with fine-grained run-time power gating., , , , , , , , , и 7 other автор(ы). ASP-DAC, стр. 87-88. IEEE, (2011)