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Wordline voltage generating system for low-power low-voltage flash memories.

, , , , , , , , and . IEEE J. Solid State Circuits, 36 (1): 55-63 (2001)

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A channel-erasing 1.8-V-only 32-Mb NOR flash EEPROM with a bitline direct sensing scheme., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 35 (11): 1648-1654 (2000)Wordline voltage generating system for low-power low-voltage flash memories., , , , , , , , and . IEEE J. Solid State Circuits, 36 (1): 55-63 (2001)A CMOS bandgap reference circuit with sub-1-V operation., , , , , , and . IEEE J. Solid State Circuits, 34 (5): 670-674 (1999)PlusDBG: Web Community Extraction Scheme Improving Both Precision and Pseudo-Recall., , and . APWeb, volume 3399 of Lecture Notes in Computer Science, page 938-943. Springer, (2005)A 44-mm2 four-bank eight-word page-read 64-Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 37 (11): 1485-1492 (2002)A 16-Mb flash EEPROM with a new self-data-refresh scheme for a sector erase operation., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 29 (4): 461-469 (April 1994)