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Disambiguation of "Hutin, Louis"

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Si MOS technology for spin-based quantum computing.

, , , , , , , , , , , , , , , , and . ESSDERC, page 12-17. IEEE, (2018)

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Ralf Hüting

Antun Hutinec

Reinhard Hüting

Jürgen Hüting

Dieter Hüting

 

Other publications of authors with the same name

Compact MEMS modeling to design full adder in Capacitive Adiabatic Logic., , , , and . ESSDERC, page 174-177. IEEE, (2018)Towards scalable silicon quantum computing., , , , , , , , , and 7 other author(s). DRC, page 1-2. IEEE, (2018)Electrical Coupling of Perpendicular Superparamagnetic Tunnel Junctions for Probabilistic Computing., , , , , , and . NANOARCH, page 16:1-16:6. ACM, (2022)Design considerations for optimization of pull-in stability margin in electrostatic N/MEM relays., , , , , and . ICICDT, page 1-4. IEEE, (2017)Robustness and Power Efficiency in Spin-Orbit Torque-Based Probabilistic Logic Circuits., , , , and . ISVLSI, page 1-6. IEEE, (2023)1024 3D-Stacked Monolithic NEMS Array with 375μm20.5mW 0.28ppm Frequency Deviation Pixel-level Readout for Zeptogram Gravimetric Sensing., , , , , , , , , and 3 other author(s). ISSCC, page 1-3. IEEE, (2022)MOS technology for quantum computing: recent progress and perspectives for scaling up., , , , , , , , , and 3 other author(s). DRC, page 1-2. IEEE, (2021)SOI CMOS technology for quantum information processing., , , , , , , , , and 5 other author(s). ICICDT, page 1-4. IEEE, (2017)RF performance of Standard, High-Resistivity and Trap-Rich Silicon substrates down to cryogenic temperature., , , , , , , , , and 1 other author(s). ESSDERC, page 148-151. IEEE, (2023)Capacitive adiabatic logic based on gap-closing MEMS devices., , , , , , and . PATMOS, page 1-6. IEEE, (2017)