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Slope only sense amplifier with 4.5ns sense delay for 8Mbit memory sector, employing in situ current monitoring with 66% write speed improvement in 40nm embedded flash for automotive.

, , , , and . ESSCIRC, page 339-342. IEEE, (2015)

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Single Supply Voltage High-Speed Semi-dynamic Level-Converting Flip-Flop with Low Power and Area Consumption., , , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 392-401. Springer, (2004)Modelling and simulation of nanomagnetic logic with cadence virtuoso using Verilog-A., , , , , and . ESSDERC, page 97-100. IEEE, (2015)A 13.56MHz class e power amplifier for inductively coupled DC supply with 95% power added efficiency (PAE)., , , , and . EURFID, page 87-93. IEEE, (2015)In-Situ Delay Characterization and Local Supply Voltage Adjustment for Compensation of Local Parametric Variations., , , , and . IEEE J. Solid State Circuits, 42 (7): 1583-1592 (2007)Analysis and compensation of the bitline multiplexer in SRAM current sense amplifiers., , and . IEEE J. Solid State Circuits, 36 (11): 1745-1755 (2001)A 90-nm CMOS Low-Power GSM/EDGE Multimedia-Enhanced Baseband Processor With 380-MHz ARM926 Core and Mixed-Signal Extensions., , , , , , , , , and 9 other author(s). IEEE J. Solid State Circuits, 42 (1): 134-144 (2007)A 1.8-V MOSFET-only ΣΔ modulator using substrate biased depletion-mode MOS capacitors in series compensation., , and . IEEE J. Solid State Circuits, 36 (7): 1041-1047 (2001)A Design Space Comparison of 6T and 8T SRAM Core-Cells., , and . PATMOS, volume 5349 of Lecture Notes in Computer Science, page 116-125. Springer, (2008)A 0.6V 100dB 5.2MHz transconductance amplifier realized in a multi-VT process., , , and . ESSCIRC, page 247-250. IEEE, (2005)Dynamic state-retention flip flop for fine-grained sleep-transistor scheme., , , , , , , , , and 2 other author(s). ESSCIRC, page 145-148. IEEE, (2005)