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Scalable Gate-Level Models for Power and Timing Analysis.

M. Badaroglu, G. der Plas, P. Wambacq, S. Donnay, G. Gielen, and H. Man. ISCAS, page 2938-2941. IEEE, (2007)

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Stéphane Klein

Stéphane Müller

Stéphane Haussler

Stéphane Clinchant

Stéphane Aubry

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High-Level Power Minimization of Analog Sensor Interface Architectures.S. Donnay, G. Gielen, and W. Sansen. Integr. Comput. Aided Eng., 5 (4): 303-314 (1998)Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients.M. Badaroglu, K. Tiri, S. Donnay, P. Wambacq, H. Man, I. Verbauwhede, and G. Gielen. DAC, page 399-404. ACM, (2002)Digital ground bounce reduction by supply current shaping and clock frequency Modulation.M. Badaroglu, P. Wambacq, G. der Plas, S. Donnay, G. Gielen, and H. Man. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (1): 65-76 (2005)OFDM versus Single Carrier with Cyclic Prefix: a system-based comparison.J. Tubbax, B. Come, L. der Perre, L. Deneire, S. Donnay, and M. Engels. VTC Fall, page 1115-1119. IEEE, (2001)Compensation of transmitter IQ imbalance for OFDM systems.J. Tubbax, B. Come, L. der Perre, S. Donnay, M. Moonen, and H. Man. ICASSP (2), page 325-328. IEEE, (2004)Digital Ground Bounce Reduction by Phase Modulation of the Clock.M. Badaroglu, P. Wambacq, G. der Plas, S. Donnay, G. Gielen, and H. Man. DATE, page 88-93. IEEE Computer Society, (2004)A Single-Package Solution for Wireless Transceivers.P. Wambacq, S. Donnay, H. Ziad, M. Engels, H. Man, and I. Bolsens. DATE, page 425-. IEEE Computer Society / ACM, (1999)Ultra wide-band body area channel model.A. Fort, C. Desset, J. Ryckaert, P. Doncker, L. Biesen, and S. Donnay. ICC, page 2840-2844. IEEE, (2005)Substrate noise immune design of an LC-tank VCO using sensitivity functions.C. Soens, G. der Plas, P. Wambacq, and S. Donnay. CICC, page 477-480. IEEE, (2005)A 328 μW 5 GHz voltage-controlled oscillator in 90 nm CMOS with high-quality thin-film post-processed inductor.D. Linten, X. Sun, G. Carchon, W. Jeamsaksiri, A. Mercha, J. Ramos, S. Jenei, L. Aspemyr, A. Scholten, P. Wambacq and 3 other author(s). CICC, page 701-704. IEEE, (2004)

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Disambiguation of "Donnay, Stéphane"

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Scalable Gate-Level Models for Power and Timing Analysis.

Please choose a person to relate this publication to

Stéphane Klein

Stéphane Müller

Stéphane Haussler

Stéphane Clinchant

Stéphane Aubry

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Donnay, Stéphane"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Scalable Gate-Level Models for Power and Timing Analysis.

Please choose a person to relate this publication to

Stéphane Klein

Stéphane Müller

Stéphane Haussler

Stéphane Clinchant

Stéphane Aubry

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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Scalable Gate-Level Models for Power and Timing Analysis.