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Disambiguation of "Sarkar, Chandan Kumar"

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Influence of channel length and high-K oxide thickness on subthreshold analog/RF performance of graded channel and gate stack DG-MOSFETs.

, , , , and . Microelectron. Reliab., (2016)

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Mtech Chandan Kumar Suri

Chandan Kumar Jana

Ananda Kumar Sarkar

Chandan Maity

Chandan Mukherjee

 

Other publications of authors with the same name

Design and Analysis of a Robust, High Speed, Energy Efficient 18 Transistor 1-bit Full Adder Cell, Modified with the Concept of MVT Scheme., , , , and . ISED, page 130-134. IEEE, (2012)A 4-bit Asynchronous Binary Search ADC for Low Power, High Speed Applications., , , , and . ISED, page 28-32. IEEE, (2012)Study of hafnium oxide deposited using Dense Plasma Focus machine for film structure and electrical properties as a MOS device., , , , and . Microelectron. Reliab., 51 (4): 751-755 (2011)A threshold voltage model for short-channel MOSFETs taking into account the varying depth of channel depletion layers around the source and drain., , and . Microelectron. Reliab., 48 (1): 17-22 (2008)Subthreshold analog/RF performance of underlap DG FETs with asymmetric source/drain extensions., , , , and . Microelectron. Reliab., 52 (11): 2572-2578 (2012)Electron transport in two dimensional electron gas formed at the heterojunction of AlxGa(1-x)N/GaN at microwave frequencies., and . Microelectron. Reliab., 50 (7): 965-970 (2010)Study on the performance of sub 100 nm LACLATI MOSFETs for digital application., , and . Microelectron. Reliab., 49 (4): 392-396 (2009)Study on effect of back oxide thickness variation in FDSOI MOSFET on analogue circuit performance., , , and . IET Circuits Devices Syst., 10 (6): 497-503 (2016)Design of High Performance 8 bit Multiplier using Vedic Multiplication Algorithm with McCMOS Technique., , , and . J. Signal Process. Syst., 76 (1): 1-9 (2014)Impact of Fin Width Scaling on RF/Analog Performance of Junctionless Accumulation-Mode Bulk FinFET., , and . JETC, 12 (4): 36:1-36:12 (2016)