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Device and Circuit Models of Monolithic InAlN/GaN NAND and NOR Logic Cells Comprising D- and E-Mode HEMTs.

A. Chvála, L. Nagy, J. Marek, J. Priesol, D. Donoval, A. Satka, M. Blaho, D. Gregusová, and J. Kuzmík. J. Circuits Syst. Comput., 28 (Supplement-1): 1940009:1-1940009:14 (2019)

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Alexander

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Comparison of Otsu's and Rosin's Methods for Threshold Determination.M. Hagara, A. Satka, O. Ondrácek, and R. Stojanovic. MECO, page 1-4. IEEE, (2023)Non-linear thermal modeling of DMOS transistor and validation using electrical measurements and FEM simulations.V. Kosel, R. Illing, M. Glavanovics, and A. Satka. Microelectron. J., 41 (12): 889-896 (2010)Characterisation of titanium disilicide thin films.A. Satka, J. Liday, R. Srnánek, A. Vincze, D. Donoval, J. Kovác, M. Veselý, and M. Michalka. Microelectron. J., 37 (11): 1389-1395 (2006)Behavior of various geometry MagFET structures.M. Daricek, M. Donoval, and A. Satka. ECCTD, page 17-20. IEEE, (2009)Characterization of MagFET structures.M. Daricek, M. Donoval, A. Satka, and T. Kosik. ICECS, page 1233-1236. IEEE, (2008)Gate leakage current in GaN-based mesa- and planar-type heterostructure field-effect transistors.J. Kovác, A. Satka, A. Chvála, D. Donoval, P. Kordos, and S. Delage. Microelectron. Reliab., 52 (7): 1323-1327 (2012)Modified algorithm of unimodal thresholding for FPGA implementation.M. Hagara, R. Stojanovic, A. Satka, P. Kubinec, and O. Ondrácek. Microprocess. Microsystems, (October 2022)Analysis of multifinger power HEMTs supported by effective 3-D device electrothermal simulation.A. Chvála, J. Marek, P. Pribytny, A. Satka, S. Stoffels, N. Posthuma, S. Decoutere, and D. Donoval. Microelectron. Reliab., (2017)Device and circuit models of InAlN/GaN D- and dual-gate E-mode HEMTs for design and characterisation of monolithic NAND logic cell.A. Chvála, L. Nagy, J. Marek, J. Priesol, D. Donoval, A. Satka, M. Blaho, D. Gregusová, and J. Kuzmík. DTIS, page 1-6. IEEE, (2018)Device and Circuit Models of Monolithic InAlN/GaN NAND and NOR Logic Cells Comprising D- and E-Mode HEMTs.A. Chvála, L. Nagy, J. Marek, J. Priesol, D. Donoval, A. Satka, M. Blaho, D. Gregusová, and J. Kuzmík. J. Circuits Syst. Comput., 28 (Supplement-1): 1940009:1-1940009:14 (2019)

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Disambiguation of "Satka, Alexander"

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Device and Circuit Models of Monolithic InAlN/GaN NAND and NOR Logic Cells Comprising D- and E-Mode HEMTs.

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Alexander

Alexander Stadler

Alexander Auch

Alexander Blecken

Alexander Gocht

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Satka, Alexander"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Device and Circuit Models of Monolithic InAlN/GaN NAND and NOR Logic Cells Comprising D- and E-Mode HEMTs.

Please choose a person to relate this publication to

Alexander

Alexander Stadler

Alexander Auch

Alexander Blecken

Alexander Gocht

Other publications of authors with the same name

Disambiguation

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Device and Circuit Models of Monolithic InAlN/GaN NAND and NOR Logic Cells Comprising D- and E-Mode HEMTs.