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A Wideband W-Band Receiver Front-End in 65-nm CMOS., , , and . IEEE J. Solid State Circuits, 43 (8): 1717-1730 (2008)A 35-GS/s, 4-Bit Flash ADC With Active Data and Clock Distribution Trees., , and . IEEE J. Solid State Circuits, 44 (6): 1709-1720 (2009)Design of a Dual W- and D-Band PLL., , , , , , and . IEEE J. Solid State Circuits, 46 (5): 1011-1022 (2011)An 18-Gb/s, Direct QPSK Modulation SiGe BiCMOS Transceiver for Last Mile Links in the 70-80 GHz Band., , , , , , and . IEEE J. Solid State Circuits, 45 (10): 1968-1980 (2010)The Invariance of Characteristic Current Densities in Nanoscale MOSFETs and Its Impact on Algorithmic Design Methodologies and Design Porting of Si(Ge) (Bi)CMOS High-Speed Building Blocks., , , , , , , , , and . IEEE J. Solid State Circuits, 41 (8): 1830-1845 (2006)A 1-Tap 40-Gb/s Look-Ahead Decision Feedback Equalizer in 0.18-$muhbox m$SiGe BiCMOS Technology., , and . IEEE J. Solid State Circuits, 41 (10): 2224-2232 (2006)A 13.2-dBm, 138-GHz I/Q RF-DAC with 64-QAM and OFDM free-space constellation formation., , , and . ESSCIRC, page 191-194. IEEE, (2017)Towards a sub-2.5V, 100-Gb/s Serial Transceiver., , , , , , , , and . CICC, page 471-478. IEEE, (2007)A 45nm SOI CMOS Class-D mm-Wave PA with >10Vpp differential swing., , , , and . ISSCC, page 88-90. IEEE, (2012)A 2x-Oversampling, 128-GS/s 5-bit Flash ADC for 64-GBaud Applications., , and . BCICTS, page 52-55. IEEE, (2018)