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Disambiguation of "Kim, Chang-Yong"

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Profile based fast noise estimation and high ISO noise reduction for digital cameras.

, , , and . Digital Photography, volume 6817 of SPIE Proceedings, page 68170B. SPIE, (2008)

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Yong Jae Chang

Yong-Ho Kim

Yong Koo Kim

Byung-Yong Kim

Yong-Gi Kim

 

Other publications of authors with the same name

A Correlation Matrix Method of Clock Partitioning for Sequential Circuit Testability., , and . Great Lakes Symposium on VLSI, page 300-. IEEE Computer Society, (1999)Multiple Faults: Modeling, Simulation and Test., , and . ASP-DAC/VLSI Design, page 592-597. IEEE Computer Society, (2002)CMOS image sensor noise reduction method for image signal processor in digital cameras and camera phones., , , and . Digital Photography, volume 6502 of SPIE Proceedings, page 65020S. SPIE, (2007)Profile based fast noise estimation and high ISO noise reduction for digital cameras., , , and . Digital Photography, volume 6817 of SPIE Proceedings, page 68170B. SPIE, (2008)Exclusive Test and its Applications to Fault Diagnosis., , , and . VLSI Design, page 143-148. IEEE Computer Society, (2003)Sequential test generators: past, present and future., and . Integr., 26 (1-2): 41-54 (1998)Combinational automatic test pattern generation for acyclic sequential circuits., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (6): 948-956 (2005)A digital ISO expansion technique for digital cameras., , , , , and . Digital Photography, volume 7537 of SPIE Proceedings, page 75370. SPIE, (2010)Studying for multiprimary LCD., , and . Color Imaging: Processing, Hardcopy, and Applications, volume 5667 of SPIE Proceedings, page 336-343. SPIE, (2005)Combinational Test Generation for Acyclic SequentialCircuits using a Balanced ATPG Model., , and . VLSI Design, page 143-148. IEEE Computer Society, (2001)