Author of the publication

DynaTAPP: dynamic timing analysis with partial path activation in sequential circuits.

, , and . EURO-DAC, page 138-141. IEEE Computer Society Press, (1992)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Improving Circuit Testability by Clock Control., , and . Great Lakes Symposium on VLSI, page 288-293. IEEE Computer Society, (1996)Leverage Redundancy in Hardware Transactional Memory to Improve Cache Reliability., , , , and . ICPP, page 60:1-60:10. ACM, (2018)Energy-efficient I/O Thread Schedulers for NVMe SSDs on NUMA., , , , , and . CCGrid, page 569-578. IEEE Computer Society / ACM, (2017)A fast fault simulation algorithm for combinational circuits., , and . ICCAD, page 166-169. IEEE Computer Society, (1988)A Novel Method to Improve the Test Efficiency of VLSI Tests., , and . ASP-DAC/VLSI Design, page 499-504. IEEE Computer Society, (2002)Predicting Fault Coverage from Probabilistic Testability.. ITC, page 803-807. IEEE Computer Society, (1985)Clock partitioning for testability., , and . Great Lakes Symposium on VLSI, page 42-46. IEEE, (1993)Table headers: An entrance to the data mine., and . ICPR, page 4065-4070. IEEE, (2016)STEM: Spatiotemporal Management of Capacity for Intra-core Last Level Caches., , and . MICRO, page 163-174. IEEE Computer Society, (2010)A nonparametric classifier for unsegmented text., , , , , , and . DRR, volume 5296 of SPIE Proceedings, page 102-108. SPIE, (2004)