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A Low-Cost Bit-Error-Rate BIST Circuit for High-Speed ADCs Based on Gray Coding.

Y. Shyu, Y. Lin, R. Chu, G. Huang, and S. Chang. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 95-A (12): 2415-2423 (2012)

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Jia-Ming Shyu

Chian-woei Shyu

M Tingart

Wen-tsi Ting

Mei-Ling Shyu

Other publications of authors with the same name

An Efficient and Effective Methodology to Control Turn-On Sequence of Power Switches for Power Gating Designs.Y. Shyu, J. Lin, C. Lin, C. Huang, and S. Chang. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (10): 1730-1743 (2016)A 12-b 40-MS/s Calibration-Free SAR ADC.C. Hsu, S. Chang, C. Huang, L. Chang, Y. Shyu, C. Hou, H. Tseng, C. Kung, and H. Hu. IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (3): 881-890 (2018)A Low-Cost Bit-Error-Rate BIST Circuit for High-Speed ADCs Based on Gray Coding.Y. Shyu, Y. Lin, R. Chu, G. Huang, and S. Chang. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 95-A (12): 2415-2423 (2012)A 0.9-V 11-bit 25-MS/s binary-search SAR ADC in 90-nm CMOS.Y. Lin, S. Chang, Y. Shyu, G. Huang, and C. Liu. A-SSCC, page 69-72. IEEE, (2011)A fast thermal-aware fixed-outline floorplanning methodology based on analytical models.J. Lin, T. Chen, Y. Chang, W. Chang, Y. Shyu, Y. Chang, and J. Lu. ICCAD, page 1:1-1:8. ACM, (2018)A Systematic Design Methodology of Asynchronous SAR ADCs.C. Huang, J. Lin, Y. Shyu, and S. Chang. IEEE Trans. Very Large Scale Integr. Syst., 24 (5): 1835-1848 (2016)Thermal-Aware Floorplanning and TSV-Planning for Mixed-Type Modules in a Fixed-Outline 3-D IC.J. Lin, W. Chang, H. Hsieh, Y. Shyu, Y. Chang, and J. Lu. IEEE Trans. Very Large Scale Integr. Syst., 29 (9): 1652-1664 (2021)Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops.Y. Shyu, J. Lin, C. Huang, C. Lin, Y. Lin, and S. Chang. IEEE Trans. Very Large Scale Integr. Syst., 21 (4): 624-635 (2013)A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS.Y. Lin, C. Liu, G. Huang, Y. Shyu, Y. Liu, and S. Chang. IEEE Trans. Circuits Syst. I Regul. Pap., 60-I (3): 570-581 (2013)Thermal-Aware Fixed-Outline Floorplanning Using Analytical Models With Thermal-Force Modulation.J. Lin, T. Chen, H. Hsieh, Y. Shyu, Y. Chang, and J. Lu. IEEE Trans. Very Large Scale Integr. Syst., 29 (5): 985-997 (2021)

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Disambiguation of "Shyu, Ya-Ting"

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A Low-Cost Bit-Error-Rate BIST Circuit for High-Speed ADCs Based on Gray Coding.

Please choose a person to relate this publication to

Jia-Ming Shyu

Chian-woei Shyu

M Tingart

Wen-tsi Ting

Mei-Ling Shyu

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Shyu, Ya-Ting"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Low-Cost Bit-Error-Rate BIST Circuit for High-Speed ADCs Based on Gray Coding.

Please choose a person to relate this publication to

Jia-Ming Shyu

Chian-woei Shyu

M Tingart

Wen-tsi Ting

Mei-Ling Shyu

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A Low-Cost Bit-Error-Rate BIST Circuit for High-Speed ADCs Based on Gray Coding.