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Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning.

, , , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (4): 645-658 (2007)

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Leakage Current Estimation of CMOS Circuit with Stack Effect., , , , and . J. Comput. Sci. Technol., 19 (5): 708-717 (2004)Partial random walk for large linear network analysis., , , and . ISCAS (5), page 173-177. IEEE, (2004)Shielding Area Optimization Under the Solution of Interconnect Crosstalk., , , and . J. Comput. Sci. Technol., 20 (6): 901-906 (2005)Algorithm for yield driven correction of layout., , , and . ISCAS (5), page 241-245. IEEE, (2004)Shielding area optimization under the solution of interconnect crosstalk., , , , , and . ISCAS (5), page 297-300. IEEE, (2004)Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building., , , and . ISCAS, page 2040-2043. IEEE, (2007)Thermal Impacts of Leakage Power in 2D/3D floorplanning., , , and . Journal of Circuits, Systems, and Computers, 19 (7): 1483-1495 (2010)Topological routing to maximize routability for package substrate., , , , , , and . DAC, page 566-569. ACM, (2008)Integrated interlayer via planning and pin assignment for 3D ICs., , , and . SLIP, page 99-104. ACM, (2009)Stairway compaction using corner block list and its applications with rectilinear blocks., , , , , and . ACM Trans. Design Autom. Electr. Syst., 9 (2): 199-211 (2004)