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Design and Analysis of an APU for Exascale Computing., , , , , , , , , and 8 other author(s). HPCA, page 85-96. IEEE Computer Society, (2017)Killi: Runtime Fault Classification to Deploy Low Voltage Caches without MBIST., , , , and . HPCA, page 304-316. IEEE, (2019)Improving DRAM Fault Characterization through Machine Learning., , , , , , , and . DSN Workshops, page 250-253. IEEE Computer Society, (2016)Evaluating the Resilience of Parallel Applications., , , , , and . DFT, page 1-6. IEEE Computer Society, (2018)On Characterizing Near-Threshold SRAM Failures in FinFET Technology., , , and . DAC, page 53:1-53:6. ACM, (2017)A scalable instruction queue design for exploiting parallelism.. University of Michigan, USA, (2004)A Scalable Instruction Queue Design Using Dependence Chains., , and . ISCA, page 318-329. IEEE Computer Society, (2002)Integrating superscalar processor components to implement register caching., , , and . ICS, page 348-357. ACM, (2001)Lifetime memory reliability data from the field., , , , , , , and . DFT, page 1-6. IEEE Computer Society, (2017)The Impact of Resource Partitioning on SMT Processors., and . IEEE PACT, page 15-26. IEEE Computer Society, (2003)