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Disambiguation of "Bjerregaard, Tobias"

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A vertically integrated and interoperable multi-vendor synthesis flow for predictable noc design in nanoscale technologies.

, , , , , and . ASP-DAC, page 337-342. IEEE, (2014)

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Wolfgang Bjerregaard

Tobias Tobias

Tobias Lentz

Binaural technology for virtual reality. TU Aachen, (2007)

Tobias Kurz

Genexpressionsanalysen in elicitierten Suspensionskulturzellen von Eschscholzia californica Cham. und Identifizierung von EcaERF2 als transkriptioneller Regulator der Alkaloidbiosynthese. Uni Halle-Wittenberg, (2009)

Tobias Balkenhol

Adaptive Digitalfilter für die aktive Schalldämmung in Röhrensystemen. Uni Paderborn, (2009)
 

Other publications of authors with the same name

A Survey of Research and Practices of Network-on-chip, and . ACM Comput. Surv., (June 2006)A vertically integrated and interoperable multi-vendor synthesis flow for predictable noc design in nanoscale technologies., , , , , and . ASP-DAC, page 337-342. IEEE, (2014)A Simple Clockless Network-on-Chip for a Commercial Audio DSP Chip., , , and . DSD, page 641-648. IEEE Computer Society, (2006)Quest for the ultimate network-on-chip: the NaNoC project., , , , , , , , and . INA-OCMC@HiPEAC, page 43-46. ACM, (2012)A Channel Library for Asynchronous Circuit Design Supporting Mixed-Mode Modeling., , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 301-310. Springer, (2004)A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip., and . ASYNC, page 34-43. IEEE Computer Society, (2005)Packetizing OCP Transactions in the MANGO Network-on-Chip., and . DSD, page 657-664. IEEE Computer Society, (2006)A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip., and . DATE, page 1226-1231. IEEE Computer Society, (2005)A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution method., , and . DATE, page 648-653. EDA Consortium, San Jose, CA, USA, (2007)SOMA: a tool for synthesizing and optimizing memory accesses in ASICs., , , and . CODES+ISSS, page 231-236. ACM, (2005)