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Performance enhancement under power constraints using heterogeneous CMOS-TFET multicores.

E. Kultursay, K. Swaminathan, V. Saripalli, V. Narayanan, M. Kandemir, and S. Datta. CODES+ISSS, page 245-254. ACM, (2012)

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P Narayanan

Hermine Narayanan

Vidya Narayanan

Narayanan Radhakrishnan

Narayanan Sundaram

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Width minimization in the Single-Electron Transistor array synthesis.C. Liu, C. Chiang, C. Huang, C. Wang, Y. Chen, S. Datta, and V. Narayanan. DATE, page 1-4. European Design and Automation Association, (2014)A Monolithic-3D SRAM Design with Enhanced Robustness and In-Memory Computation Support.S. Srinivasa, A. Ramanathan, X. Li, W. Chen, F. Hsueh, C. Yang, C. Shen, J. Shieh, S. Gupta, M. Chang and 3 other author(s). ISLPED, page 34:1-34:6. ACM, (2018)Noise Aware Power Adaptive Partitioned Deep Networks for Mobile Visual Assist Platforms.P. Zientara, J. Sampson, and V. Narayanan. SoCC, page 186-191. IEEE, (2018)Using complete system simulation to characterize SPECjvm98 benchmarks.T. Li, L. John, N. Vijaykrishnan, A. Sivasubramaniam, J. Sabarinathan, and A. Murthy. ICS, page 22-33. ACM, (2000)A task-oriented vision system.Y. Xiao, K. Irick, J. Sampson, V. Narayanan, and C. Zhang. ACM Great Lakes Symposium on VLSI, page 181-186. ACM, (2014)A comparative study of power efficient SRAM designs.J. Hezavei, N. Vijaykrishnan, and M. Irwin. ACM Great Lakes Symposium on VLSI, page 117-122. ACM, (2000)Java Runtime Systems: Characterization and Architectural Implications.R. Radhakrishnan, N. Vijaykrishnan, L. John, A. Sivasubramaniam, J. Rubio, and J. Sabarinathan. IEEE Trans. Computers, 50 (2): 131-146 (2001)X-VS: Crossbar-Based Processing-in-Memory Architecture for Video Summarization.N. Challapalle, M. Chandran, S. Rampalli, and V. Narayanan. ISVLSI, page 592-597. IEEE, (2020)Power Analysis Attack Resistance Engineering by Dynamic Voltage and Frequency Scaling.S. Yang, P. Gupta, M. Wolf, D. Serpanos, V. Narayanan, and Y. Xie. ACM Trans. Embed. Comput. Syst., 11 (3): 62:1-62:16 (2012)An Accuracy Tunable Non-Boolean Co-Processor Using Coupled Nano-Oscillators.N. Gala, S. Krithivasan, W. Tsai, X. Li, V. Narayanan, and V. Kamakoti. ACM J. Emerg. Technol. Comput. Syst., 14 (1): 1:1-1:28 (2018)

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Disambiguation of "Narayanan, Vijaykrishnan"

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Performance enhancement under power constraints using heterogeneous CMOS-TFET multicores.

Please choose a person to relate this publication to

P Narayanan

Hermine Narayanan

Vidya Narayanan

Narayanan Radhakrishnan

Narayanan Sundaram

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Narayanan, Vijaykrishnan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Performance enhancement under power constraints using heterogeneous CMOS-TFET multicores.

Please choose a person to relate this publication to

P Narayanan

Hermine Narayanan

Vidya Narayanan

Narayanan Radhakrishnan

Narayanan Sundaram

Other publications of authors with the same name

Disambiguation

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DOI
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Performance enhancement under power constraints using heterogeneous CMOS-TFET multicores.