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Disambiguation of "Shin, Jinuk Luke"

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The next-generation 64b SPARC core in a T4 SoC processor.

, , , , , , , , , , , , , , and . ISSCC, page 60-62. IEEE, (2012)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Dong-Shin Shin

Jeonghun Shin

Kirche als Weltforum: zum Dialogverständnis in kirchlichen Dokumenten seit dem Zweiten Vatikanischen Konzil. Uni München, (2009)

Werner Luke

Alfred Lüke

Wolfgang Lüke

 

Other publications of authors with the same name

AI SoC Design Challenges in the Foundation Model Era., , , , , , , , , and 9 other author(s). CICC, page 1-8. IEEE, (2023)Asymmetric Frequency Locked Loop (AFLL) for adaptive clock generation in a 28nm SPARC M6 processor., , , , , , , and . A-SSCC, page 373-376. IEEE, (2014)A dual-core 64b ultraSPARC microprocessor for dense server applications., , , , and . DAC, page 673-677. ACM, (2004)A 40nm 16-core 128-thread CMT SPARC SoC processor., , , , , , , , , and 3 other author(s). ISSCC, page 98-99. IEEE, (2010)The UltraSPARC T1 Processor: CMT Reliability., , and . CICC, page 555-562. IEEE, (2006)Bandwidth and power management of glueless 8-socket SPARC T5 system., , , and . ISSCC, page 58-59. IEEE, (2013)Session 4 overview: Processors: High-performance digital subcommittee., and . ISSCC, page 68-69. IEEE, (2015)A Power-Efficient High-Throughput 32-Thread SPARC Processor., , , , , , , and . ISSCC, page 295-304. IEEE, (2006)A 40 nm 16-Core 128-Thread SPARC SoC Processor., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 46 (1): 131-144 (2011)SambaNova SN10 RDU: A 7nm Dataflow Architecture to Accelerate Software 2.0., , and . ISSCC, page 350-352. IEEE, (2022)