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A PLL-based synthesizer for tunable digital clock generation in a continuous-time SigmaDelta A/D converter.

J. Segundo, L. Quintanilla, J. Álvarez, L. Enríquez, J. Hernández-Mangas, and J. Vicente. Integr., 42 (1): 24-33 (2009)

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Jesús Miguel Carnicer Álvarez

Julián Jesús Fernández Arias

Pedro Miguel d' Jesús Montilva

Rodrigo Álvarez

Jesús Araiza

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A PLL-based synthesizer for tunable digital clock generation in a continuous-time SigmaDelta A/D converter.J. Segundo, L. Quintanilla, J. Álvarez, L. Enríquez, J. Hernández-Mangas, and J. Vicente. Integr., 42 (1): 24-33 (2009)Design of a switched opamp-based bandpass filter in a 0.35 μm CMOS technology.L. Quintanilla, J. Álvarez, L. Enríquez, J. Vicente, J. Barbolla, D. Vázquez, and A. Rueda. ICECS, page 29-32. IEEE, (2002)Stable high-order delta-sigma digital-to-analog converters.P. Kiss, J. Álvarez, D. Li, and V. Boccuzzi. IEEE Trans. Circuits Syst. I Regul. Pap., 51-I (1): 200-205 (2004)Nonlinearity correction for multibit ΔΣ DACs.J. Álvarez, P. Kiss, V. Boccuzzi, L. Quintanilla, L. Enríquez, J. Vicente, D. Bisbal, J. Pablo, and J. Barbolla. IEEE Trans. Circuits Syst. I Regul. Pap., 52-I (6): 1033-1041 (2005)Stable high-order delta-sigma DACS.P. Kiss, J. Álvarez, and D. Li. ISCAS (1), page 985-988. IEEE, (2003)A 32-mW 320-MHz continuous-time complex delta-sigma ADC for multi-mode wireless-LAN receivers.J. Álvarez, P. Kiss, V. Prodanov, V. Boccuzzi, M. Banu, D. Bisbal, J. Pablo, L. Quintanilla, and J. Barbolla. IEEE J. Solid State Circuits, 41 (2): 339-351 (2006)Effect of Finite amplifier Bandwidth and excess Loop Delay in a Parallel CT δς ADC for OFDM UWB receivers.L. Quintanilla, J. Álvarez, J. Segundo, L. Enríquez, J. Hernández-Mangas, and J. Vicente. J. Circuits Syst. Comput., (2013)A 1.2 V, 130 nm CMOS parallel continuous-time ΣΔ ADC for OFDM UWB receivers.J. Segundo, J. Álvarez, L. Quintanilla, L. Enríquez, J. Hernández-Mangas, and J. Vicente. Microelectron. J., 43 (4): 288-297 (2012)A parallel, CT-ΔΣ based ADC for OFDM UWB receivers in 130 nm CMOS.J. Segundo, J. Álvarez, L. Quintanilla, L. Enríquez, J. Hernández-Mangas, and J. Vicente. ICECS, page 406-409. IEEE, (2011)Parallel Continuous-Time DeltaSigma ADC for OFDM UWB Receivers.J. Álvarez, L. Quintanilla, J. Segundo, L. Enríquez, J. Vicente, and J. Hernández-Mangas. IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (7): 1478-1487 (2009)

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A PLL-based synthesizer for tunable digital clock generation in a continuous-time SigmaDelta A/D converter.

Please choose a person to relate this publication to

Jesús Miguel Carnicer Álvarez

Julián Jesús Fernández Arias

Pedro Miguel d' Jesús Montilva

Rodrigo Álvarez

Jesús Araiza

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Álvarez, Jesús Arias"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A PLL-based synthesizer for tunable digital clock generation in a continuous-time SigmaDelta A/D converter.

Please choose a person to relate this publication to

Jesús Miguel Carnicer Álvarez

Julián Jesús Fernández Arias

Pedro Miguel d' Jesús Montilva

Rodrigo Álvarez

Jesús Araiza

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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A PLL-based synthesizer for tunable digital clock generation in a continuous-time SigmaDelta A/D converter.