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A parallel, CT-ΔΣ based ADC for OFDM UWB receivers in 130 nm CMOS.

J. Segundo, J. Álvarez, L. Quintanilla, L. Enríquez, J. Hernández-Mangas, and J. Vicente. ICECS, page 406-409. IEEE, (2011)

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Werner Luis

Pia Luislampe

Mathieu Luisier

Werner Luis

Other publications of authors with the same name

Nonlinearity correction for multibit ΔΣ DACs.J. Álvarez, P. Kiss, V. Boccuzzi, L. Quintanilla, L. Enríquez, J. Vicente, D. Bisbal, J. Pablo, and J. Barbolla. IEEE Trans. Circuits Syst. I Regul. Pap., 52-I (6): 1033-1041 (2005)Automated Machine Learning & Tuning with FLAML.C. Wang, Q. Wu, X. Liu, and L. Quintanilla. KDD, page 4828-4829. ACM, (2022)Parallel Continuous-Time DeltaSigma ADC for OFDM UWB Receivers.J. Álvarez, L. Quintanilla, J. Segundo, L. Enríquez, J. Vicente, and J. Hernández-Mangas. IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (7): 1478-1487 (2009)Detailed analysis of the effect of a hysteretic quantizer in a multibit, Sigma-Delta modulator.L. Quintanilla, J. Álvarez, J. Segundo, L. Enríquez, J. Hernández-Mangas, and J. Vicente. Microelectron. J., 42 (1): 148-157 (2011)Design of a CMOS fully differential switched-opamp for SC circuits at very low power supply voltages.J. Álvarez, L. Quintanilla, L. Enríquez, J. Vicente, J. Barbolla, D. Vázquez, and A. Rueda. ICECS, page 1545-1548. IEEE, (2001)A PLL-based synthesizer for tunable digital clock generation in a continuous-time SigmaDelta A/D converter.J. Segundo, L. Quintanilla, J. Álvarez, L. Enríquez, J. Hernández-Mangas, and J. Vicente. Integr., 42 (1): 24-33 (2009)Design of a switched opamp-based bandpass filter in a 0.35 μm CMOS technology.L. Quintanilla, J. Álvarez, L. Enríquez, J. Vicente, J. Barbolla, D. Vázquez, and A. Rueda. ICECS, page 29-32. IEEE, (2002)A 32-mW 320-MHz continuous-time complex delta-sigma ADC for multi-mode wireless-LAN receivers.J. Álvarez, P. Kiss, V. Prodanov, V. Boccuzzi, M. Banu, D. Bisbal, J. Pablo, L. Quintanilla, and J. Barbolla. IEEE J. Solid State Circuits, 41 (2): 339-351 (2006)Effect of Finite amplifier Bandwidth and excess Loop Delay in a Parallel CT δς ADC for OFDM UWB receivers.L. Quintanilla, J. Álvarez, J. Segundo, L. Enríquez, J. Hernández-Mangas, and J. Vicente. J. Circuits Syst. Comput., (2013)A 1.2 V, 130 nm CMOS parallel continuous-time ΣΔ ADC for OFDM UWB receivers.J. Segundo, J. Álvarez, L. Quintanilla, L. Enríquez, J. Hernández-Mangas, and J. Vicente. Microelectron. J., 43 (4): 288-297 (2012)

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Disambiguation of "Quintanilla, Luis"

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A parallel, CT-ΔΣ based ADC for OFDM UWB receivers in 130 nm CMOS.

Please choose a person to relate this publication to

Werner Luis

Pia Luislampe

Mathieu Luisier

Werner Luis

Werner Luis

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Quintanilla, Luis"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A parallel, CT-ΔΣ based ADC for OFDM UWB receivers in 130 nm CMOS.

Please choose a person to relate this publication to

Werner Luis

Pia Luislampe

Mathieu Luisier

Werner Luis

Werner Luis

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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A parallel, CT-ΔΣ based ADC for OFDM UWB receivers in 130 nm CMOS.