Author of the publication

mm2and 6T HBST-TRAM-Based 2D Data-Reuse Architecture.

J. Yue, R. Liu, W. Sun, Z. Yuan, Z. Wang, Y. Tu, Y. Chen, A. Ren, Y. Wang, M. Chang, X. Li, H. Yang, and Y. Liu. ISSCC, page 138-140. IEEE, (2019)

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Angelika Ning

Jing Ning

Werner Yu-fung Ning

Hans Ningel

Michael Ningler

Other publications of authors with the same name

A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors.X. Si, R. Liu, S. Yu, R. Liu, C. Hsieh, K. Tang, Q. Li, M. Chang, J. Chen, Y. Tu and 6 other author(s). IEEE J. Solid State Circuits, 55 (1): 189-202 (2020)A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors.Y. Chiu, Z. Zhang, J. Chen, X. Si, R. Liu, Y. Tu, J. Su, W. Huang, J. Wang, W. Wei and 8 other author(s). IEEE J. Solid State Circuits, 55 (10): 2790-2801 (2020)A 65nm 0.39-to-140.3TOPS/W 1-to-12b Unified Neural Network Processor Using Block-Circulant-Enabled Transpose-Domain Acceleration with 8.1 × Higher TOPS/mm2and 6T HBST-TRAM-Based 2D Data-Reuse Architecture.J. Yue, R. Liu, W. Sun, Z. Yuan, Z. Wang, Y. Tu, Y. Chen, A. Ren, Y. Wang, M. Chang and 3 other author(s). ISSCC, page 138-140. IEEE, (2019)Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips.J. Su, X. Si, Y. Chou, T. Chang, W. Huang, Y. Tu, R. Liu, P. Lu, T. Liu, J. Wang and 15 other author(s). IEEE J. Solid State Circuits, 57 (2): 609-624 (2022)15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips.J. Su, X. Si, Y. Chou, T. Chang, W. Huang, Y. Tu, R. Liu, P. Lu, T. Liu, J. Wang and 13 other author(s). ISSCC, page 240-242. IEEE, (2020)Monolithic-3D Integration Augmented Design Techniques for Computing in SRAMs.S. Srinivasa, W. Chen, Y. Tu, M. Chang, J. Sampson, and V. Narayanan. ISCAS, page 1-5. IEEE, (2019)STICKER-T: An Energy-Efficient Neural Network Processor Using Block-Circulant Algorithm and Unified Frequency-Domain Acceleration.J. Yue, Y. Liu, R. Liu, W. Sun, Z. Yuan, Y. Tu, Y. Chen, A. Ren, Y. Wang, M. Chang and 2 other author(s). IEEE J. Solid State Circuits, 56 (6): 1936-1948 (2021)A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning.X. Si, J. Chen, Y. Tu, W. Huang, J. Wang, Y. Chiu, W. Wei, S. Wu, X. Sun, R. Liu and 6 other author(s). ISSCC, page 396-398. IEEE, (2019)A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors.Z. Zhang, J. Chen, X. Si, Y. Tu, J. Su, W. Huang, J. Wang, W. Wei, Y. Chiu, J. Hong and 6 other author(s). A-SSCC, page 217-218. IEEE, (2019)A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips.X. Si, Y. Tu, W. Huang, J. Su, P. Lu, J. Wang, T. Liu, S. Wu, R. Liu, Y. Chou and 11 other author(s). IEEE J. Solid State Circuits, 56 (9): 2817-2831 (2021)

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Disambiguation of "Tu, Yung-Ning"