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Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction.

, , , and . MICRO, page 219-230. ACM/IEEE Computer Society, (2002)

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Architecture of a Hypercube Supercomputer., , and . ICPP, page 653-660. IEEE Computer Society Press, (1986)Virtual memory in contemporary microprocessors., and . IEEE Micro, 18 (4): 60-75 (1998)PicoServer: Using 3D stacking technology to build energy efficient servers., , , , , and . JETC, 4 (4): 16:1-16:34 (2008)Quantitative analysis and optimization techniques for on-chip cache leakage power., , and . IEEE Trans. Very Large Scale Integr. Syst., 13 (10): 1147-1156 (2005)Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation., , , , , , , and . IEEE Micro, 24 (6): 10-20 (2004)Centip3De: A 3930DMIPS/W configurable near-threshold 3D stacked system with 64 ARM Cortex-M3 cores., , , , , , , , , and 5 other author(s). ISSCC, page 190-192. IEEE, (2012)A comparison of two pipeline organizations., and . MICRO, page 153-161. ACM / IEEE Computer Society, (1994)Power: A First Class Design Constraint for Future Architecture and Automation.. HiPC, volume 1970 of Lecture Notes in Computer Science, page 215-224. Springer, (2000)ChipLock: support for secure microarchitectures., , and . SIGARCH Comput. Archit. News, 33 (1): 134-143 (2005)The limits of instruction level parallelism in SPEC95 applications., , , and . SIGARCH Comput. Archit. News, 27 (1): 31-34 (1999)