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Disambiguation of "Parvais, Bertrand"

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Modeling FinFET metal gate stack resistance for 14nm node and beyond.

, , , , , , , , and . ICICDT, page 1-4. IEEE, (2015)

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Joachim Bertrand

Bertrand Hirl

Bertrand Gloddek

Bertrand Malmendier

Jessica Bertrand

 

Other publications of authors with the same name

A 42 mW 200 fs-Jitter 60 GHz Sub-Sampling PLL in 40 nm CMOS., , , , , and . IEEE J. Solid State Circuits, 50 (9): 2025-2036 (2015)A low-power radio chipset in 40nm LP CMOS with beamforming for 60GHz high-data-rate wireless communication., , , , , , , , , and 4 other author(s). ISSCC, page 236-237. IEEE, (2013)A Composite AlGaN/cGaN Back Barrier for mm-Wave GaN-on-Si HEMTs., , , , , , , , and . ESSDERC, page 152-155. IEEE, (2023)Back-gate bias effect on UTBB-FDSOI non-linearity performance., , , , , , and . ESSDERC, page 148-151. IEEE, (2017)Reliability and Variability of Advanced CMOS Devices at Cryogenic Temperatures., , , , , , , , , and . IRPS, page 1-6. IEEE, (2020)A low-power 57-to-66GHz transceiver in 40nm LP CMOS with -17dB EVM at 7Gb/s., , , , , , , , , and 2 other author(s). ISSCC, page 268-270. IEEE, (2012)Design of a 28 GHz differential GaAs power amplifier with capacitive neutralization for 5G mmwave applications., , , , , , , and . NEWCAS, page 1-4. IEEE, (2019)21.4 A 42mW 230fs-jitter sub-sampling 60GHz PLL in 40nm CMOS., , , , , and . ISSCC, page 366-367. IEEE, (2014)Solid state qubits: how learning from CMOS fabrication can speed-up progress in Quantum Computing., , , , , , , , , and 19 other author(s). VLSI Circuits, page 1-2. IEEE, (2021)Understanding the memory window in 1T-FeFET memories: a depolarization field perspective., , , , , , , and . IMW, page 1-4. IEEE, (2021)