( en | de | ru )

 

Disambiguation of "Thean, Aaron"

Author of the publication

copydeleteadd this publication to your clipboard
Modeling FinFET metal gate stack resistance for 14nm node and beyond.

, , , , , , , , and . ICICDT, page 1-4. IEEE, (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Kurt Aaron

Siegfried Aaron

Else Aaron

Aaron Rosmarin

Aaron Bogan

 

Other publications of authors with the same name

NBTI in Si0.55Ge0.45 cladding p-FinFETs: Porting the superior reliability from planar to 3D architectures., , , , , , , , , and . IRPS, page 2. IEEE, (2015)FinFET stressor efficiency on alternative wafer and channel orientations for the 14 nm node and below., , , , and . ICICDT, page 1-4. IEEE, (2015)Area and routing efficiency of SWD circuits compared to advanced CMOS., , , , , , , , and . ICICDT, page 1-4. IEEE, (2015)Holisitic device exploration for 7nm node., , , , , , , , , and 5 other author(s). CICC, page 1-5. IEEE, (2015)Dimensioning for power and performance under 10nm: The limits of FinFETs scaling., , , , , , , and . ICICDT, page 1-4. IEEE, (2015)Modeling FinFET metal gate stack resistance for 14nm node and beyond., , , , , , , , and . ICICDT, page 1-4. IEEE, (2015)Computer Modeling of Silicon Quantum Dot Floating -Gate Flash Memory Devices. University of Illinois Urbana-Champaign, USA, (2001)Low-frequency noise assessment of the transport mechanisms in SiGe channel bulk FinFETs., , , , , , , , , and 1 other author(s). ESSDERC, page 330-333. IEEE, (2012)Non-uniform strain in lattice-mismatched heterostructure tunnel field-effect transistors., , , , , , and . ESSDERC, page 412-415. IEEE, (2016)System-level assessment and area evaluation of Spin Wave logic circuits., , , , , , , and . NANOARCH, page 25-30. IEEE Computer Society/ACM, (2014)