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Disambiguation of "Mocuta, Anda"

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Modeling FinFET metal gate stack resistance for 14nm node and beyond.

, , , , , , , , and . ICICDT, page 1-4. IEEE, (2015)

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Ahmad Anda

Anda Napo

László Anda

Valér anda

Muzaffer Andaç

 

Other publications of authors with the same name

Nonparabolicity and confinement effects of IIIV materials in novel transistors., , and . ICICDT, page 1-3. IEEE, (2015)Assessment of SiGe quantum well transistors for DRAM peripheral applications., , , , , , , , , and 1 other author(s). ICICDT, page 1-4. IEEE, (2015)Modeling FinFET metal gate stack resistance for 14nm node and beyond., , , , , , , , and . ICICDT, page 1-4. IEEE, (2015)Direct Temperature Measurement for VLSI Circuits and 3-D Modeling of Self-Heating in Sub-0.13 mum SOI Technologies., , , , , and . VLSI Design, page 697-702. IEEE Computer Society, (2005)CDM-Time Domain Turn-on Transient of ESD Diodes in Bulk FinFET and GAA NW Technologies., , , , , , , , , and . IRPS, page 1-7. IEEE, (2019)Non-uniform strain in lattice-mismatched heterostructure tunnel field-effect transistors., , , , , , and . ESSDERC, page 412-415. IEEE, (2016)Impact of fin shape variability on device performance towards 10nm node., , , , , , , , , and 3 other author(s). ICICDT, page 1-4. IEEE, (2015)SRAM designs for 5nm node and beyond: Opportunities and challenges., , , , , and . ICICDT, page 1-4. IEEE, (2017)Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications., , , , , , , , , and 2 other author(s). DAC, page 13. ACM, (2019)Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7., , , , , , , , , and 2 other author(s). ESSDERC, page 256-259. IEEE, (2017)